Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
betaFALSE build_version2086221
date_generatedWed Mar 28 20:55:19 2018 os_platformWIN64
product_versionVivado v2017.4 (64-bit) project_ida644815ed7d4416ca615aacfde50162d
project_iteration8 random_id1c2bbde5b38859fd812adcb1cb388e12
registration_id1c2bbde5b38859fd812adcb1cb388e12 route_designTRUE
target_devicexc7z020 target_familyzynq
target_packageclg400 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i5-4570 CPU @ 3.20GHz cpu_speed3200 MHz
os_nameMicrosoft Windows 8 or later , 64-bit os_releasemajor release (build 9200)
system_ram34.000 GB total_processors1

vivado_usage
gui_handlers
addrepositoryinfodialog_ok=2 basedialog_cancel=6 basedialog_ok=39 basedialog_yes=2
clkconfigtreetablepanel_clk_config_tree_table=1 coretreetablepanel_core_tree_table=44 createnewdiagramdialog_design_name=2 filesetpanel_file_set_panel_tree=10
flownavigatortreepanel_flow_navigator_tree=36 flownavigatorview_collapse_next_level=3 flownavigatorview_expand_next_level=1 gensettingtreetablepanel_gen_setting_tree_table=2
gettingstartedview_create_new_project=1 gettingstartedview_open_project=1 hfolderchooserhelpers_up_one_level=1 instancemenu_floorplanning=6
ipstatussectionpanel_upgrade_selected=1 mainmenumgr_export=18 mainmenumgr_file=32 mainmenumgr_help=2
mainmenumgr_import=17 mainmenumgr_open_recent_file=16 mainmenumgr_open_recent_project=16 mainmenumgr_report=7
mainmenumgr_tools=14 mainmenumgr_view=2 messagewithoptiondialog_dont_show_this_dialog_again=2 netlisttreeview_netlist_tree=22
newexporthardwaredialog_include_bitstream=2 newipwizard_create_new_axi4_ip_create_axi4=2 newipwizard_name_myip=4 pacommandnames_auto_update_hier=3
pacommandnames_close_project=1 pacommandnames_create_top_hdl=1 pacommandnames_exit=1 pacommandnames_export_hardware=6
pacommandnames_goto_implemented_design=1 pacommandnames_ip_packager_wizard=2 pacommandnames_launch_hardware=5 pacommandnames_regenerate_layout=18
pacommandnames_save_rsb_design=5 pacommandnames_toggle_view_nav=1 pacommandnames_zoom_in=2 partchooser_boards=3
paviews_device=2 planaheadtab_refresh_ip_catalog=2 planaheadtab_show_flow_navigator=1 primitivesmenu_color=4
primitivesmenu_highlight_leaf_cells=8 projectnamechooser_choose_project_location=3 projectnamechooser_project_name=1 projectsummaryutilizationpanel_project_summary_utilization_panel_tabbed=1
projecttab_reload=2 rdicommands_custom_commands=5 rdicommands_settings=5 rsbapplyautomationbar_run_block_automation=1
rsbapplyautomationbar_run_connection_automation=6 saveprojectutils_cancel=1 saveprojectutils_save=1 selectmenu_highlight=5
settingsdialog_options_tree=1 settingsdialog_project_tree=5 settingsprojectiprepositorypage_add_repository=3 simpleoutputproductdialog_generate_output_products_immediately=1
srcmenu_ip_hierarchy=3 syntheticagettingstartedview_recent_projects=2 systembuilderview_add_ip=16 systembuilderview_expand_collapse=1
systemtab_show_ip_status=1 taskbanner_close=3 tclconsoleview_tcl_console_code_editor=7 touchpointsurveydialog_no=1
java_command_handlers
closeproject=1 createblockdesign=1 createtophdl=1 customizersbblock=3
editdelete=3 editundo=6 fileexit=1 ippackagerwizardhandler=2
newexporthardware=6 newlaunchhardware=5 newproject=1 openblockdesign=8
openproject=1 regeneratersblayout=18 runbitgen=9 runsynthesis=1
saversbdesign=5 showview=3 toggleviewnavigator=1 toolssettings=7
upgradeip=1 viewtaskimplementation=6 zoomin=2
other_data
guimode=5
project_data
constraintsetcount=0 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=1 export_simulation_ies=1
export_simulation_modelsim=1 export_simulation_questa=1 export_simulation_riviera=1 export_simulation_vcs=1
export_simulation_xsim=1 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=2 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=7 totalsynthesisruns=7

unisim_transformation
post_unisim_transformation
bibuf=130 bufg=1 carry4=43 dsp48e1=2
fdre=2020 fdse=67 gnd=64 lut1=159
lut2=220 lut3=517 lut4=327 lut5=405
lut6=626 muxf7=18 ps7=1 ramb18e1=18
ramb36e1=3 srl16e=19 srlc32e=47 vcc=67
pre_unisim_transformation
bibuf=130 bufg=1 carry4=43 dsp48e1=2
fdre=2020 fdse=67 gnd=64 lut1=159
lut2=220 lut3=517 lut4=327 lut5=405
lut6=626 muxf7=18 ps7=1 ramb18e1=18
ramb36e1=3 srl16e=19 srlc32e=47 vcc=67

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=18 bram_ports_newly_gated=2 bram_ports_total=42 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=2046 srls_augmented=0
srls_newly_gated=0 srls_total=66

ip_statistics
AES_Full/1
c_s_axi_crtls_addr_width=10 c_s_axi_crtls_data_width=32 core_container=NA iptotal=1
x_ipcorerevision=1803282048 x_iplanguage=VERILOG x_iplibrary=hls x_ipname=AES_Full
x_ipproduct=Vivado 2017.4 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=1.0
IP_Integrator/1
bdsource=USER core_container=NA da_axi4_cnt=3 da_ps7_cnt=1
iptotal=1 maxhierdepth=0 numblks=12 numhdlrefblks=0
numhierblks=5 numhlsblks=2 numnonxlnxblks=0 numpkgbdblks=0
numreposblks=7 numsysgenblks=0 synth_mode=OOC_per_IP x_iplanguage=VERILOG
x_iplibrary=BlockDiagram x_ipname=Zynq_CPU x_ipvendor=xilinx.com x_ipversion=1.00.a
axi_crossbar_v2_1_16_axi_crossbar/1
c_axi_addr_width=32 c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1
c_axi_data_width=32 c_axi_id_width=1 c_axi_protocol=2 c_axi_ruser_width=1
c_axi_supports_user_signals=0 c_axi_wuser_width=1 c_connectivity_mode=0 c_family=zynq
c_m_axi_addr_width=0x000000100000001000000010 c_m_axi_base_addr=0x0000000043c200000000000043c100000000000043c00000 c_m_axi_read_connectivity=0x000000010000000100000001 c_m_axi_read_issuing=0x000000010000000100000001
c_m_axi_secure=0x000000000000000000000000 c_m_axi_write_connectivity=0x000000010000000100000001 c_m_axi_write_issuing=0x000000010000000100000001 c_num_addr_ranges=1
c_num_master_slots=3 c_num_slave_slots=1 c_r_register=1 c_s_axi_arb_priority=0x00000000
c_s_axi_base_id=0x00000000 c_s_axi_read_acceptance=0x00000001 c_s_axi_single_thread=0x00000001 c_s_axi_thread_id_width=0x00000000
c_s_axi_write_acceptance=0x00000001 core_container=NA iptotal=1 x_ipcorerevision=16
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=axi_crossbar x_ipproduct=Vivado 2017.4
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=2.1
axi_protocol_converter_v2_1_15_axi_protocol_converter/1
c_axi_addr_width=32 c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1
c_axi_data_width=32 c_axi_id_width=12 c_axi_ruser_width=1 c_axi_supports_read=1
c_axi_supports_user_signals=0 c_axi_supports_write=1 c_axi_wuser_width=1 c_family=zynq
c_ignore_id=0 c_m_axi_protocol=2 c_s_axi_protocol=1 c_translation_mode=2
core_container=NA iptotal=1 x_ipcorerevision=15 x_iplanguage=VERILOG
x_iplibrary=ip x_ipname=axi_protocol_converter x_ipproduct=Vivado 2017.4 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=2.1
hls_ip_2017_4/1
core_container=NA hls_input_arch=others hls_input_clock=10.000000 hls_input_fixed=0
hls_input_float=0 hls_input_part=xc7z020clg400-1 hls_input_type=cxx hls_syn_clock=6.669000
hls_syn_dsp=0 hls_syn_ff=1216 hls_syn_lat=-1 hls_syn_lut=6185
hls_syn_mem=24 hls_syn_tpt=none iptotal=1
hls_ip_2017_4/2
core_container=NA hls_input_arch=others hls_input_clock=10.000000 hls_input_fixed=0
hls_input_float=0 hls_input_part=xc7z020clg400-1 hls_input_type=cxx hls_syn_clock=7.380000
hls_syn_dsp=1 hls_syn_ff=112 hls_syn_lat=0 hls_syn_lut=168
hls_syn_mem=0 hls_syn_tpt=none iptotal=1
hls_multiplier/1
c_s_axi_crtls_addr_width=6 c_s_axi_crtls_data_width=32 core_container=NA iptotal=1
x_ipcorerevision=1803151152 x_iplanguage=VERILOG x_iplibrary=hls x_ipname=hls_multiplier
x_ipproduct=Vivado 2017.4 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=1.0
proc_sys_reset/1
c_aux_reset_high=0 c_aux_rst_width=4 c_ext_reset_high=0 c_ext_rst_width=4
c_family=zynq c_num_bus_rst=1 c_num_interconnect_aresetn=1 c_num_perp_aresetn=1
c_num_perp_rst=1 core_container=NA iptotal=1 x_ipcorerevision=12
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=proc_sys_reset x_ipproduct=Vivado 2017.4
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=5.0
processing_system7_v5.5_user_configuration/1
core_container=NA iptotal=1 pcw_apu_clk_ratio_enable=6:2:1 pcw_apu_peripheral_freqmhz=650
pcw_armpll_ctrl_fbdiv=26 pcw_can0_grp_clk_enable=0 pcw_can0_peripheral_clksrc=External pcw_can0_peripheral_enable=0
pcw_can0_peripheral_freqmhz=-1 pcw_can1_grp_clk_enable=0 pcw_can1_peripheral_clksrc=External pcw_can1_peripheral_enable=0
pcw_can1_peripheral_freqmhz=-1 pcw_can_peripheral_clksrc=IO PLL pcw_can_peripheral_freqmhz=100 pcw_cpu_cpu_pll_freqmhz=1300.000
pcw_cpu_peripheral_clksrc=ARM PLL pcw_crystal_peripheral_freqmhz=50 pcw_dci_peripheral_clksrc=DDR PLL pcw_dci_peripheral_freqmhz=10.159
pcw_ddr_ddr_pll_freqmhz=1050.000 pcw_ddr_hpr_to_critical_priority_level=15 pcw_ddr_hprlpr_queue_partition=HPR(0)/LPR(32) pcw_ddr_lpr_to_critical_priority_level=2
pcw_ddr_peripheral_clksrc=DDR PLL pcw_ddr_port0_hpr_enable=0 pcw_ddr_port1_hpr_enable=0 pcw_ddr_port2_hpr_enable=0
pcw_ddr_port3_hpr_enable=0 pcw_ddr_write_to_critical_priority_level=2 pcw_ddrpll_ctrl_fbdiv=21 pcw_enet0_enet0_io=MIO 16 .. 27
pcw_enet0_grp_mdio_enable=1 pcw_enet0_peripheral_clksrc=IO PLL pcw_enet0_peripheral_enable=1 pcw_enet0_peripheral_freqmhz=1000 Mbps
pcw_enet0_reset_enable=1 pcw_enet0_reset_io=MIO 9 pcw_enet1_grp_mdio_enable=0 pcw_enet1_peripheral_clksrc=IO PLL
pcw_enet1_peripheral_enable=0 pcw_enet1_peripheral_freqmhz=1000 Mbps pcw_enet1_reset_enable=0 pcw_enet_reset_polarity=Active Low
pcw_fclk0_peripheral_clksrc=IO PLL pcw_fclk1_peripheral_clksrc=IO PLL pcw_fclk2_peripheral_clksrc=IO PLL pcw_fclk3_peripheral_clksrc=IO PLL
pcw_fpga0_peripheral_freqmhz=100 pcw_fpga1_peripheral_freqmhz=50 pcw_fpga2_peripheral_freqmhz=50 pcw_fpga3_peripheral_freqmhz=50
pcw_fpga_fclk0_enable=1 pcw_fpga_fclk1_enable=0 pcw_fpga_fclk2_enable=0 pcw_fpga_fclk3_enable=0
pcw_gpio_emio_gpio_enable=0 pcw_gpio_mio_gpio_enable=1 pcw_gpio_mio_gpio_io=MIO pcw_gpio_peripheral_enable=0
pcw_i2c0_grp_int_enable=0 pcw_i2c0_peripheral_enable=0 pcw_i2c0_reset_enable=0 pcw_i2c1_grp_int_enable=0
pcw_i2c1_peripheral_enable=0 pcw_i2c1_reset_enable=0 pcw_i2c_reset_polarity=Active Low pcw_io_io_pll_freqmhz=1000.000
pcw_iopll_ctrl_fbdiv=20 pcw_irq_f2p_mode=DIRECT pcw_m_axi_gp0_freqmhz=10 pcw_m_axi_gp1_freqmhz=10
pcw_nand_cycles_t_ar=1 pcw_nand_cycles_t_clr=1 pcw_nand_cycles_t_rc=11 pcw_nand_cycles_t_rea=1
pcw_nand_cycles_t_rr=1 pcw_nand_cycles_t_wc=11 pcw_nand_cycles_t_wp=1 pcw_nand_grp_d8_enable=0
pcw_nand_peripheral_enable=0 pcw_nor_cs0_t_ceoe=1 pcw_nor_cs0_t_pc=1 pcw_nor_cs0_t_rc=11
pcw_nor_cs0_t_tr=1 pcw_nor_cs0_t_wc=11 pcw_nor_cs0_t_wp=1 pcw_nor_cs0_we_time=0
pcw_nor_cs1_t_ceoe=1 pcw_nor_cs1_t_pc=1 pcw_nor_cs1_t_rc=11 pcw_nor_cs1_t_tr=1
pcw_nor_cs1_t_wc=11 pcw_nor_cs1_t_wp=1 pcw_nor_cs1_we_time=0 pcw_nor_grp_a25_enable=0
pcw_nor_grp_cs0_enable=0 pcw_nor_grp_cs1_enable=0 pcw_nor_grp_sram_cs0_enable=0 pcw_nor_grp_sram_cs1_enable=0
pcw_nor_grp_sram_int_enable=0 pcw_nor_peripheral_enable=0 pcw_nor_sram_cs0_t_ceoe=1 pcw_nor_sram_cs0_t_pc=1
pcw_nor_sram_cs0_t_rc=11 pcw_nor_sram_cs0_t_tr=1 pcw_nor_sram_cs0_t_wc=11 pcw_nor_sram_cs0_t_wp=1
pcw_nor_sram_cs0_we_time=0 pcw_nor_sram_cs1_t_ceoe=1 pcw_nor_sram_cs1_t_pc=1 pcw_nor_sram_cs1_t_rc=11
pcw_nor_sram_cs1_t_tr=1 pcw_nor_sram_cs1_t_wc=11 pcw_nor_sram_cs1_t_wp=1 pcw_nor_sram_cs1_we_time=0
pcw_override_basic_clock=0 pcw_pcap_peripheral_clksrc=IO PLL pcw_pcap_peripheral_freqmhz=200 pcw_pjtag_peripheral_enable=0
pcw_preset_bank0_voltage=LVCMOS 3.3V pcw_preset_bank1_voltage=LVCMOS 1.8V pcw_qspi_grp_fbclk_enable=1 pcw_qspi_grp_fbclk_io=MIO 8
pcw_qspi_grp_io1_enable=0 pcw_qspi_grp_single_ss_enable=1 pcw_qspi_grp_single_ss_io=MIO 1 .. 6 pcw_qspi_grp_ss1_enable=0
pcw_qspi_internal_highaddress=0xFCFFFFFF pcw_qspi_peripheral_clksrc=IO PLL pcw_qspi_peripheral_enable=1 pcw_qspi_peripheral_freqmhz=200
pcw_qspi_qspi_io=MIO 1 .. 6 pcw_s_axi_acp_freqmhz=10 pcw_s_axi_gp0_freqmhz=10 pcw_s_axi_gp1_freqmhz=10
pcw_s_axi_hp0_data_width=64 pcw_s_axi_hp0_freqmhz=10 pcw_s_axi_hp1_data_width=64 pcw_s_axi_hp1_freqmhz=10
pcw_s_axi_hp2_data_width=64 pcw_s_axi_hp2_freqmhz=10 pcw_s_axi_hp3_data_width=64 pcw_s_axi_hp3_freqmhz=10
pcw_sd0_grp_cd_enable=1 pcw_sd0_grp_cd_io=MIO 47 pcw_sd0_grp_pow_enable=0 pcw_sd0_grp_wp_enable=0
pcw_sd0_peripheral_enable=1 pcw_sd0_sd0_io=MIO 40 .. 45 pcw_sd1_grp_cd_enable=0 pcw_sd1_grp_pow_enable=0
pcw_sd1_grp_wp_enable=0 pcw_sd1_peripheral_enable=0 pcw_sdio_peripheral_clksrc=IO PLL pcw_sdio_peripheral_freqmhz=50
pcw_single_qspi_data_mode=x4 pcw_smc_peripheral_clksrc=IO PLL pcw_smc_peripheral_freqmhz=100 pcw_spi0_grp_ss0_enable=0
pcw_spi0_grp_ss1_enable=0 pcw_spi0_grp_ss2_enable=0 pcw_spi0_peripheral_enable=0 pcw_spi1_grp_ss0_enable=0
pcw_spi1_grp_ss1_enable=0 pcw_spi1_grp_ss2_enable=0 pcw_spi1_peripheral_enable=0 pcw_spi_peripheral_clksrc=IO PLL
pcw_spi_peripheral_freqmhz=166.666666 pcw_tpiu_peripheral_clksrc=External pcw_tpiu_peripheral_freqmhz=200 pcw_trace_grp_16bit_enable=0
pcw_trace_grp_2bit_enable=0 pcw_trace_grp_32bit_enable=0 pcw_trace_grp_4bit_enable=0 pcw_trace_grp_8bit_enable=0
pcw_trace_peripheral_enable=0 pcw_ttc0_clk0_peripheral_clksrc=CPU_1X pcw_ttc0_clk0_peripheral_freqmhz=133.333333 pcw_ttc0_clk1_peripheral_clksrc=CPU_1X
pcw_ttc0_clk1_peripheral_freqmhz=133.333333 pcw_ttc0_clk2_peripheral_clksrc=CPU_1X pcw_ttc0_clk2_peripheral_freqmhz=133.333333 pcw_ttc0_peripheral_enable=0
pcw_ttc1_clk0_peripheral_clksrc=CPU_1X pcw_ttc1_clk0_peripheral_freqmhz=133.333333 pcw_ttc1_clk1_peripheral_clksrc=CPU_1X pcw_ttc1_clk1_peripheral_freqmhz=133.333333
pcw_ttc1_clk2_peripheral_clksrc=CPU_1X pcw_ttc1_clk2_peripheral_freqmhz=133.333333 pcw_ttc1_peripheral_enable=0 pcw_ttc_peripheral_freqmhz=50
pcw_uart0_baud_rate=115200 pcw_uart0_grp_full_enable=0 pcw_uart0_peripheral_enable=1 pcw_uart0_uart0_io=MIO 14 .. 15
pcw_uart1_baud_rate=115200 pcw_uart1_grp_full_enable=0 pcw_uart1_peripheral_enable=0 pcw_uart_peripheral_clksrc=IO PLL
pcw_uart_peripheral_freqmhz=100 pcw_uiparam_ddr_adv_enable=0 pcw_uiparam_ddr_al=0 pcw_uiparam_ddr_bank_addr_count=3
pcw_uiparam_ddr_bl=8 pcw_uiparam_ddr_board_delay0=0.223 pcw_uiparam_ddr_board_delay1=0.212 pcw_uiparam_ddr_board_delay2=0.085
pcw_uiparam_ddr_board_delay3=0.092 pcw_uiparam_ddr_bus_width=16 Bit pcw_uiparam_ddr_cl=7 pcw_uiparam_ddr_clock_0_length_mm=25.8
pcw_uiparam_ddr_clock_0_package_length=80.4535 pcw_uiparam_ddr_clock_0_propogation_delay=160 pcw_uiparam_ddr_clock_1_length_mm=25.8 pcw_uiparam_ddr_clock_1_package_length=80.4535
pcw_uiparam_ddr_clock_1_propogation_delay=160 pcw_uiparam_ddr_clock_2_length_mm=0 pcw_uiparam_ddr_clock_2_package_length=80.4535 pcw_uiparam_ddr_clock_2_propogation_delay=160
pcw_uiparam_ddr_clock_3_length_mm=0 pcw_uiparam_ddr_clock_3_package_length=80.4535 pcw_uiparam_ddr_clock_3_propogation_delay=160 pcw_uiparam_ddr_clock_stop_en=0
pcw_uiparam_ddr_col_addr_count=10 pcw_uiparam_ddr_cwl=6 pcw_uiparam_ddr_device_capacity=4096 MBits pcw_uiparam_ddr_dq_0_length_mm=16.5
pcw_uiparam_ddr_dq_0_package_length=98.503 pcw_uiparam_ddr_dq_0_propogation_delay=160 pcw_uiparam_ddr_dq_1_length_mm=18 pcw_uiparam_ddr_dq_1_package_length=68.5855
pcw_uiparam_ddr_dq_1_propogation_delay=160 pcw_uiparam_ddr_dq_2_length_mm=0 pcw_uiparam_ddr_dq_2_package_length=90.295 pcw_uiparam_ddr_dq_2_propogation_delay=160
pcw_uiparam_ddr_dq_3_length_mm=0 pcw_uiparam_ddr_dq_3_package_length=103.977 pcw_uiparam_ddr_dq_3_propogation_delay=160 pcw_uiparam_ddr_dqs_0_length_mm=15.6
pcw_uiparam_ddr_dqs_0_package_length=105.056 pcw_uiparam_ddr_dqs_0_propogation_delay=160 pcw_uiparam_ddr_dqs_1_length_mm=18.8 pcw_uiparam_ddr_dqs_1_package_length=66.904
pcw_uiparam_ddr_dqs_1_propogation_delay=160 pcw_uiparam_ddr_dqs_2_length_mm=0 pcw_uiparam_ddr_dqs_2_package_length=89.1715 pcw_uiparam_ddr_dqs_2_propogation_delay=160
pcw_uiparam_ddr_dqs_3_length_mm=0 pcw_uiparam_ddr_dqs_3_package_length=113.63 pcw_uiparam_ddr_dqs_3_propogation_delay=160 pcw_uiparam_ddr_dqs_to_clk_delay_0=0.040
pcw_uiparam_ddr_dqs_to_clk_delay_1=0.058 pcw_uiparam_ddr_dqs_to_clk_delay_2=-0.009 pcw_uiparam_ddr_dqs_to_clk_delay_3=-0.033 pcw_uiparam_ddr_dram_width=16 Bits
pcw_uiparam_ddr_ecc=Disabled pcw_uiparam_ddr_enable=1 pcw_uiparam_ddr_freq_mhz=525 pcw_uiparam_ddr_high_temp=Normal (0-85)
pcw_uiparam_ddr_memory_type=DDR 3 pcw_uiparam_ddr_partno=MT41J256M16 RE-125 pcw_uiparam_ddr_row_addr_count=15 pcw_uiparam_ddr_speed_bin=DDR3_1066F
pcw_uiparam_ddr_t_faw=40.0 pcw_uiparam_ddr_t_ras_min=35.0 pcw_uiparam_ddr_t_rc=48.91 pcw_uiparam_ddr_t_rcd=7
pcw_uiparam_ddr_t_rp=7 pcw_uiparam_ddr_train_data_eye=1 pcw_uiparam_ddr_train_read_gate=1 pcw_uiparam_ddr_train_write_level=1
pcw_uiparam_ddr_use_internal_vref=0 pcw_usb0_peripheral_enable=1 pcw_usb0_peripheral_freqmhz=60 pcw_usb0_reset_enable=1
pcw_usb0_reset_io=MIO 46 pcw_usb0_usb0_io=MIO 28 .. 39 pcw_usb1_peripheral_enable=0 pcw_usb1_peripheral_freqmhz=60
pcw_usb1_reset_enable=0 pcw_usb_reset_polarity=Active Low pcw_use_cross_trigger=0 pcw_use_m_axi_gp0=1
pcw_use_m_axi_gp1=0 pcw_use_s_axi_acp=0 pcw_use_s_axi_gp0=0 pcw_use_s_axi_gp1=0
pcw_use_s_axi_hp0=0 pcw_use_s_axi_hp1=0 pcw_use_s_axi_hp2=0 pcw_use_s_axi_hp3=0
pcw_wdt_peripheral_clksrc=CPU_1X pcw_wdt_peripheral_enable=0 pcw_wdt_peripheral_freqmhz=133.333333
processing_system7_v5_5_processing_system7/1
c_dm_width=4 c_dq_width=32 c_dqs_width=4 c_emio_gpio_width=64
c_en_emio_enet0=0 c_en_emio_enet1=0 c_en_emio_pjtag=0 c_en_emio_trace=0
c_fclk_clk0_buf=TRUE c_fclk_clk1_buf=FALSE c_fclk_clk2_buf=FALSE c_fclk_clk3_buf=FALSE
c_gp0_en_modifiable_txn=1 c_gp1_en_modifiable_txn=1 c_include_acp_trans_check=0 c_include_trace_buffer=0
c_irq_f2p_mode=DIRECT c_m_axi_gp0_enable_static_remap=0 c_m_axi_gp0_id_width=12 c_m_axi_gp0_thread_id_width=12
c_m_axi_gp1_enable_static_remap=0 c_m_axi_gp1_id_width=12 c_m_axi_gp1_thread_id_width=12 c_mio_primitive=54
c_num_f2p_intr_inputs=1 c_package_name=clg400 c_ps7_si_rev=PRODUCTION c_s_axi_acp_aruser_val=31
c_s_axi_acp_awuser_val=31 c_s_axi_acp_id_width=3 c_s_axi_gp0_id_width=6 c_s_axi_gp1_id_width=6
c_s_axi_hp0_data_width=64 c_s_axi_hp0_id_width=6 c_s_axi_hp1_data_width=64 c_s_axi_hp1_id_width=6
c_s_axi_hp2_data_width=64 c_s_axi_hp2_id_width=6 c_s_axi_hp3_data_width=64 c_s_axi_hp3_id_width=6
c_trace_buffer_clock_delay=12 c_trace_buffer_fifo_size=128 c_trace_internal_width=2 c_trace_pipeline_width=8
c_use_axi_nonsecure=0 c_use_default_acp_user_val=0 c_use_m_axi_gp0=1 c_use_m_axi_gp1=0
c_use_s_axi_acp=0 c_use_s_axi_gp0=0 c_use_s_axi_gp1=0 c_use_s_axi_hp0=0
c_use_s_axi_hp1=0 c_use_s_axi_hp2=0 c_use_s_axi_hp3=0 core_container=NA
iptotal=1 use_trace_data_edge_detector=0 x_ipcorerevision=6 x_iplanguage=VERILOG
x_iplibrary=ip x_ipname=processing_system7 x_ipproduct=Vivado 2017.4 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=5.5
rtl_multiplier_v1_0/1
c_s00_axi_addr_width=4 c_s00_axi_data_width=32 core_container=NA iptotal=1
x_ipcorerevision=2 x_iplanguage=VERILOG x_iplibrary=user x_ipname=rtl_multiplier
x_ipproduct=Vivado 2017.4 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=1.0

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
dpip-1=4 dpop-1=2 dpop-2=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-waived=default::[not_specified]

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -l=default::[not_specified] -name=default::[not_specified] -no_propagation=default::[not_specified]
-return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified] -vid=default::[not_specified]
-xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=8to11 (8 to 11 Layers) board_selection=medium (10"x10") bram=0.019341 clocks=0.007890
confidence_level_clock_activity=High confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium
confidence_level_io_activity=High confidence_level_overall=Medium customer=TBD customer_class=TBD
devstatic=0.136248 die=xc7z020clg400-1 dsp=0.000000 dsp_output_toggle=12.500000
dynamic=1.293377 effective_thetaja=11.5 enable_probability=0.990000 family=zynq
ff_toggle=12.500000 flow_state=routed heatsink=none input_toggle=12.500000
junction_temp=41.5 (C) logic=0.003385 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000
mgtavcc_total_current=0.000000 mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000
mgtavtt_total_current=0.000000 mgtavtt_voltage=1.200000 mgtvccaux_dynamic_current=0.000000 mgtvccaux_static_current=0.000000
mgtvccaux_total_current=0.000000 mgtvccaux_voltage=1.800000 netlist_net_matched=NA off-chip_power=0.000000
on-chip_power=1.429625 output_enable=1.000000 output_load=5.000000 output_toggle=12.500000
package=clg400 pct_clock_constrained=3.000000 pct_inputs_defined=0 platform=nt64
process=typical ps7=1.255906 ram_enable=50.000000 ram_write=50.000000
read_saif=False set/reset_probability=0.000000 signal_rate=False signals=0.006855
simulation_file=None speedgrade=-1 static_prob=False temp_grade=commercial
thetajb=7.4 (C/W) thetasa=0.0 (C/W) toggle_rate=False user_board_temp=25.0 (C)
user_effective_thetaja=11.5 user_junc_temp=41.5 (C) user_thetajb=7.4 (C/W) user_thetasa=0.0 (C/W)
vccadc_dynamic_current=0.000000 vccadc_static_current=0.020000 vccadc_total_current=0.020000 vccadc_voltage=1.800000
vccaux_dynamic_current=0.000000 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000
vccaux_io_voltage=1.800000 vccaux_static_current=0.014222 vccaux_total_current=0.014222 vccaux_voltage=1.800000
vccbram_dynamic_current=0.001414 vccbram_static_current=0.001484 vccbram_total_current=0.002898 vccbram_voltage=1.000000
vccint_dynamic_current=0.036057 vccint_static_current=0.013825 vccint_total_current=0.049882 vccint_voltage=1.000000
vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000 vcco12_total_current=0.000000 vcco12_voltage=1.200000
vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000 vcco135_total_current=0.000000 vcco135_voltage=1.350000
vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000 vcco15_total_current=0.000000 vcco15_voltage=1.500000
vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000 vcco18_total_current=0.000000 vcco18_voltage=1.800000
vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000 vcco25_total_current=0.000000 vcco25_voltage=2.500000
vcco33_dynamic_current=0.000000 vcco33_static_current=0.000000 vcco33_total_current=0.000000 vcco33_voltage=3.300000
vcco_ddr_dynamic_current=0.351705 vcco_ddr_static_current=0.002000 vcco_ddr_total_current=0.353705 vcco_ddr_voltage=1.500000
vcco_mio0_dynamic_current=0.001750 vcco_mio0_static_current=0.001000 vcco_mio0_total_current=0.002750 vcco_mio0_voltage=3.300000
vcco_mio1_dynamic_current=0.002187 vcco_mio1_static_current=0.001000 vcco_mio1_total_current=0.003187 vcco_mio1_voltage=1.800000
vccpaux_dynamic_current=0.026155 vccpaux_static_current=0.010330 vccpaux_total_current=0.036485 vccpaux_voltage=1.800000
vccpint_dynamic_current=0.646808 vccpint_static_current=0.027245 vccpint_total_current=0.674053 vccpint_voltage=1.000000
vccpll_dynamic_current=0.013749 vccpll_static_current=0.003000 vccpll_total_current=0.016749 vccpll_voltage=1.800000
version=2017.4

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=1 bufgctrl_util_percentage=3.13
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=16 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=8 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=16 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=4 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=4 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsp48e1_only_used=2 dsps_available=220 dsps_fixed=0 dsps_used=2
dsps_util_percentage=0.91
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=1 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=1 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=1 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=140 block_ram_tile_fixed=0 block_ram_tile_used=12 block_ram_tile_util_percentage=8.57
ramb18_available=280 ramb18_fixed=0 ramb18_used=18 ramb18_util_percentage=6.43
ramb18e1_only_used=18 ramb36_fifo_available=140 ramb36_fifo_fixed=0 ramb36_fifo_used=3
ramb36_fifo_util_percentage=2.14 ramb36e1_only_used=3
primitives
bibuf_functional_category=IO bibuf_used=130 bufg_functional_category=Clock bufg_used=1
carry4_functional_category=CarryLogic carry4_used=43 dsp48e1_functional_category=Block Arithmetic dsp48e1_used=2
fdce_functional_category=Flop & Latch fdce_used=4 fdre_functional_category=Flop & Latch fdre_used=1980
fdse_functional_category=Flop & Latch fdse_used=66 lut1_functional_category=LUT lut1_used=44
lut2_functional_category=LUT lut2_used=220 lut3_functional_category=LUT lut3_used=505
lut4_functional_category=LUT lut4_used=324 lut5_functional_category=LUT lut5_used=403
lut6_functional_category=LUT lut6_used=632 muxf7_functional_category=MuxFx muxf7_used=18
ps7_functional_category=Specialized Resource ps7_used=1 ramb18e1_functional_category=Block Memory ramb18e1_used=18
ramb36e1_functional_category=Block Memory ramb36e1_used=3 srl16e_functional_category=Distributed Memory srl16e_used=19
srlc32e_functional_category=Distributed Memory srlc32e_used=47
slice_logic
f7_muxes_available=26600 f7_muxes_fixed=0 f7_muxes_used=18 f7_muxes_util_percentage=0.07
f8_muxes_available=13300 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=53200 lut_as_logic_fixed=0
lut_as_logic_used=1735 lut_as_logic_util_percentage=3.26 lut_as_memory_available=17400 lut_as_memory_fixed=0
lut_as_memory_used=62 lut_as_memory_util_percentage=0.36 lut_as_shift_register_fixed=0 lut_as_shift_register_used=62
register_as_flip_flop_available=106400 register_as_flip_flop_fixed=0 register_as_flip_flop_used=2050 register_as_flip_flop_util_percentage=1.93
register_as_latch_available=106400 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=53200 slice_luts_fixed=0 slice_luts_used=1797 slice_luts_util_percentage=3.38
slice_registers_available=106400 slice_registers_fixed=0 slice_registers_used=2050 slice_registers_util_percentage=1.93
fully_used_lut_ff_pairs_fixed=1.93 fully_used_lut_ff_pairs_used=180 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0
lut_as_logic_available=53200 lut_as_logic_fixed=0 lut_as_logic_used=1735 lut_as_logic_util_percentage=3.26
lut_as_memory_available=17400 lut_as_memory_fixed=0 lut_as_memory_used=62 lut_as_memory_util_percentage=0.36
lut_as_shift_register_fixed=0 lut_as_shift_register_used=62 lut_ff_pairs_with_one_unused_flip_flop_fixed=62 lut_ff_pairs_with_one_unused_flip_flop_used=412
lut_ff_pairs_with_one_unused_lut_output_fixed=412 lut_ff_pairs_with_one_unused_lut_output_used=406 lut_flip_flop_pairs_available=53200 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=625 lut_flip_flop_pairs_util_percentage=1.17 slice_available=13300 slice_fixed=0
slice_used=746 slice_util_percentage=5.61 slicel_fixed=0 slicel_used=484
slicem_fixed=0 slicem_used=262 unique_control_sets_used=134 using_o5_and_o6_fixed=134
using_o5_and_o6_used=4 using_o5_output_only_fixed=4 using_o5_output_only_used=0 using_o6_output_only_fixed=0
using_o6_output_only_used=58
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

router
usage
actual_expansions=3264885 bogomips=0 bram18=18 bram36=3
bufg=0 bufr=0 congestion_level=0 ctrls=134
dsp=2 effort=2 estimated_expansions=3344784 ff=2050
global_clocks=1 high_fanout_nets=2 iob=0 lut=2008
movable_instances=4583 nets=6118 pins=30229 pll=0
router_runtime=0.000000 router_timing_driven=1 threads=2 timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7z020clg400-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=Zynq_CPU_wrapper -verilog_define=default::[not_specified]
usage
elapsed=00:00:38s hls_ip=0 memory_gain=515.672MB memory_peak=788.957MB